1. Field of the Invention
The present invention relates to an ESD (Electro-Static Discharge) protection circuit, and more particularly, to an ESD protection circuit which can improve an ESD protection capability.
2. Background of the Related Art
In general, because static electricity which affects a device reliability is a momentary high voltage that can give an influence to any place around it, a countermeasure against the electro-static discharge is very important. Though there was no problem caused by the static electricity even if no particular countermeasure against the ESD is provided when a large sized device is used, presently the countermeasure against the ESD becomes one of important condition of quality guarantee as causes of product failure are increased due to the size reduction and the increased number of pins according to the trend of packing devices to a high density and providing many pins. As the countermeasure of a semiconductor chip against such a static electricity, a protection circuit is inserted between outer pins which come to contact with the static electricity and an inner circuit, so that the inner circuit can be protected against the high static electricity and be maintained at an appropriate voltage during the static electricity passes through the protection circuit, and particularly, the protection circuit should be designed within a range in which no influence is given to a product performance. Due to this reason, there have been studies on an output terminal protection circuit use of a device having the protection circuit applied thereto is restricted due to output characteristics of the device, rather than on an input terminal protection circuit which can be designed and used without any restriction.
In the meantime, a DRAM, fabricated as CMOS, is involved in decrease of a breakdown voltage of a junction, as a device packing density is increased as the generation progresses, and particularly, the input terminal and the output terminal are susceptible to the static electricity.
There are two kinds of electro-static discharge.
First one is an electro-static discharge occurred when the DRAM, assembled in a form of package, passes through a handler lane for testing before shipment, called a machine mode, which has a low voltage, approx. 250V, but has a small impedance with a relatively great amount of electric charge.
Second one is an electro-static discharge coming from the static electricity induced in a human body when a user""s hand is come into contact with the DRAM, called a human body mode, having a high voltage of approx. 2000V with a great impedance.
In order to protect the DRAM from breakage following an inflow of such static electricity, a variety of input protection circuit is provided in the DRAM, that employs a method in which a high voltage pulse, or a high current pulse is not lead into the inner circuit, but lead to wiring with a large amount of metal line, such as ground of power line.
A related art ESD protection circuit will be explained with reference to the attached drawings. FIG. 1 illustrates a circuit showing a related art ESD protection circuit.
Referring to FIG. 1, the related art ESD protection circuit is provided with a transistor 11 connected to an input pad (PAD) 10 for discharging an ESD charge upon reception, a capacitor 12 and a first resistor 13 connected to the input pad 10 for applying a gate voltage to a gate of the transistor 11 when the input pad receives the ESD charge for improving a bipolar driving capability of the transistor 11, and a second resistor 14 for delaying transmission of the ESD charge received at the input pad PAD into the inner circuit. The transistor 11 has a drain connected to the input pad (PAD) and a source connected to a ground terminal Vss. The capacitor 12 and the first resistor 13 are connected in series between the input pad 10 and the ground terminal Vss. A gate of the transistor 11 is connected to a contact xe2x80x98Axe2x80x99 between the capacitor 12 and the first resistor 13.
The operation of the aforementioned related art ESD protection circuit will be explained.
Upon reception of an ESD charge (approx. 200Vxcx9c3000V) at the input pad 10, a bias is provided to the gate of the transistor 11 through the capacitor 12 connected to the input pad. Then, the bias provided to the gate of the transistor 11 drops a breakdown voltage of the transistor 11, assisting the transistor 11 operative in a bipolar quickly for discharging the ESD charge received at the input pad. In this instance, because much current is discharged through the transistor 11, which lowers a breakdown voltage of the transistor 11, if a gate voltage in the transistor 11 is high over 2V, a current should be discharged through the first resistor 13, to maintain the gate voltage within 0.7xcx9c2V. If the voltage to the gate of the transistor 11 is over 2V, the transistor 11 is not operative normally, causing an effective ESD charge discharge impossible.
However, the related art ESD protection circuit has the following problems.
Because the gate voltage fluctuates with the ESD voltage provided to the capacitor and the resistor connected in series between the input pad and the ground terminal, it is difficult to optimize (0.7xcx9c2V) a capacitance and a resistance provided to the gate of the transistor, so that the ESD protection circuit is operative well in different modes, such as HBM (Human Body Mode), MM (Machine Mode), and CDM (Charged Device Mode).
Accordingly, the present invention is directed to an ESD protection circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an ESD protection circuit which can minimize fluctuation of a gate voltage with an ESD input voltage, for improving an ESD protection capability.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the ESD protection circuit includes a first transistor connected to an input pad for discharging an ESD charge, a capacitor and a diode connected to the input pad for applying a gate voltage to a gate of the first transistor to improve a bipolar driving capability of the first transistor, a second transistor for controlling drive of the first transistor when the chip is operative, and a resistor for delaying transmission of an ESD charge to an inner circuit when the ESD charge is received at the input pad.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.